(IP uses avs_clk or reconfig_xcvr_clk internally). To indicate the reset status of the SIP link layer. ![]() (IP use avs_clk or reconfig_xcvr_clk internally) ![]() To User to indicate that the IP is fully in reset. User is required to assert this reset if rx_avs_rst_n is asserted. Out of reset completion indicates by deassertion of rx_rst_ack_n. Reset sequence completion indicated by assertion rx_rst_ack_n.ĭeassertion triggers out-of-reset sequence. Async Assertion and Deassertion.Īssertion triggers reset sequence to MAC and PHY(Tile). ![]() To sample SYSREF correctly, the core PLL must provide the rxlink_clk signal and must be configured as normal operating mode.įrom User. This clock is equal to RX data rate divided by 40.įor Subclass 1, you cannot use the output of rxphy_clk signal as rxlink_clk signal. RX link clock signal used by the Avalon® streaming interface.
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